The use of EEPROM Semiconductor memories has grown considerably in recent years. A typical EEPROM memory device contains a two-dimensional array of memory cells. Each cell is associated with one bit of memory. The number of cells in a typical array is a function of the size of the array. Thus, in a 256K bit memory, there will typically be 512 columns of cells, each column in turn containing 512 cells. That is, there will be 512 columns and 512 rows of cells.
Each cell in a memory array comprises a place where information can be stored. By causing a memory cell to conduct or not conduct when it is tested for conduction during a read mode, the bit of memory associated with that cell can be caused to contain a "0" or "1" in binary code. The conditions in the cell which determine whether the cell will conduct or not conduct during the read mode are set during a write mode. The process in which these conditions are set is often called "writing to" the cell. The process of determining what binary code is stored in the cell, carried on during the read mode, is often called "reading from" the cell.
Writing to, and reading from, the memory cells is accomplished by changing the inputs to various transistors within the cell at various times. Each column of memory cells in an array of cells has associated with it a bit line, which bit line is connected to each cell in the column. Likewise, each row of memory cells in an EEPROM memory cell array has associated with it a word line, which word line is connected to each cell in the row. Thus, any particular cell in the array can be identified by referring to the word line that is associated with the row in which that cell is located and the bit line associated with the column in which that cell is located. Since the array is two-dimensional, each such selection will refer to a unique cell.
In order to place data to be stored into a memory cell onto the appropriate bit line, each bit line has data input means associated with it. In the conventional array, these data input means are associated in groups of eight, eight bits comprising a byte. In practice, the data input means into the various bit lines are operatively connected to data input buffers, which route incoming data into the appropriate bit line within the appropriate byte and into the appropriate cell on the appropriate word line.
In order to read the memory cell, each bit line is operatively connected to a sense amplifier. The sense amplifier detects the flow or non-flow of current in the bit line when a semiconductor memory cell is read. It then produces and transmits a signal to an output buffer, the signal's amplitude depending upon whether current is detected or not detected when the cell is read. The output buffer is operatively connected to an input/output pin "I/O pin") which transmits the data from the multitude of cells in a semiconductor memory array.
In the conventional method of loading data into a semiconductor memory array, data is loaded a byte at a time. This method of writing data is called byte mode programming. In byte mode programming, the byte to be loaded is addressed, data to be loaded into the selected byte is loaded into the data-in buffer, the particular byte that has been selected is cleared, and the selected cells within the byte are written to according to the data in the data-in buffer. It can be seen that being limited to writing one byte at a time then means that it takes a considerable amount of time to write an entire 256K bit memory array.
It is desired to build an apparatus that is capable of programming an entire row in a memory array at one time. It is desired to build an apparatus by which the information stored at any particular bit in a memory array row can be changed without changing the information stored in the other bits in the memory array row.
The word line associated with any particular memory array row is called a "page boundary," and any cell within the row associated with that page boundary is "within the page boundary." It is desired to be able to write to any or all cells within a particular page boundary in one write period. This is called page mode programming, since an entire page may be written at once. It can be seen to one skilled in the art that since there are, in a 256K bit memory array, only 512 pages as opposed to 4,096 bytes, then page mode programming can be much faster than byte mode programming.
In page mode programming, a temporary storage means, usually a flip-flop, is associated with each bit line in the memory array. In loading, data to be loaded to a cell located on a particular bit line is transmitted to the appropriate bit line through the y-pass device associated with that bit line. The data to be loaded is then stored in the flip-flop associated with that particular bit line. All cells to be loaded within the particular page boundary are then cleared, and the entire page associated with a particular word line is written. This is repeated for different pages as many times as desired in any order desired until all of the cells in which new information is desired to be stored have been programmed with the desired information.
The use of the flip-flop associated with the memory array bit line, however, creates a problem. Because of inherent capacitance on each bit line in a memory array, after the read mode charge can get trapped on the bit line of an "unselected cell." An unselected cell being a cell into which it is not desired to load new data. If a write mode then follows the read mode, the trapped charge on the bit line can be felt at the flip-flop input during loading (at the beginning sequence of the write mode), thus causing the flip-flop output to go high, even though it was desired that the flip-flop output go low. Then, during the completion of the write mode, the memory cell may be written as if the memory cell were supposed to store a binary "0" (which corresponds to a high flip-flip output), when it actually was desired to store a binary "1" in the memory cell (corresponding to a low flip-flop output).